The present invention is directed to an integrated circuit (IC) chip for providing signals having different timing edges.
As is well known, it is often necessary to be able to create signals on an IC chip having different edge placements. Typically, such timing edges are provided by using delay elements to delay signals with respect to one another and by using logic functions to obtain different pulse widths. However, providing these delays and logic functions on an IC chip presents a number of problems. One problem which arises is a result of the difficulty of providing relatively large delays on an IC chip. The reason is that on-chip delays are severely affected by unpredictable processing variations as well as by voltage and temperature, which can cause the resulting delay provided to vary by as much as .+-.60%. Thus, when a large delay is required to be provided on an IC chip, this .+-.60% variation will be significant and may not be tolerable. A typical known solution is to provide this required long delay circuitry off-chip where accuracy can be more precisely controlled. However, this has the severe disadvantage of requiring more parts, more board space, and more expense.
An example of the problem associated with providing a relatively long on-chip delay on an IC chip is illustrated by the graphs in FIG. 1.
Graph A in FIG. 1 illustrates a typical clock C having a clock cycle time T with rising clock edges occurring at times T1 and T3, and falling clock edges occurring at times T2 and T4.
Graph B in FIG. 1 illustrates a FIRST DELAYED SIGNAL S1 produced by delaying clock C by an on-chip delay d1 which provides a relatively small delay (e.g., d1=0.10T). It is assumed in Graph B that d1 varies by ABOUT .+-.40% of d1, as indicated by .DELTA.d1.
Graph C in FIG. 1 illustrates a SECOND DELAYED SIGNAL S2 produced by delaying clock C by an on-chip delay d2 which provides a relatively large delay (e.g., d2=9T/10). Similar to d1 in Graph B, it is assumed in Graph C that d2 varies by about .+-.40% of d2, as indicated by .DELTA.d2.
As shown by Graph B in FIG. 1, the effect of .DELTA.d1 on the timing edges provided by S1 is relatively small and can easily be tolerated. This will be evident by noting that, for d1=0.10T, .DELTA.d1 will only amount to about 0.08T.
However, as shown by Graph C in FIG. 1, the effect of .DELTA.d2 on the timing edges of S2 is intolerable, since it can cause the rising edge of S2 to occur in the next clock cycle (after T3). This will be evident by noting that, for d2=0.09T, .DELTA.d2 will amount to about 0.72T. This will cause the rising clock edge of S2 to occur at about 1.26T (0.09T+0.36T), which is greater than the clock cycle time T. Note that this occurred assuming that .DELTA.d2 varies by only .+-.40% . Since this variation may typically be .+-.60% in the worst case, the provision of other than relatively small delays on a chip can present a serious timing problem. This is a primary reason why the prior art normally provides relatively long delays (such as those greater than T/2) off-chip where delay variations can be better controlled.
Another problem which arises in creating IC chip signals having different edge placements occurs because different logic functions are required to produce signals having different pulse widths. Since logic elements used to perform these different logic functions typically introduce different propagation delays, critical timing requirements may be compromised. For example, since a conventional OR gate may typically provide a different propagation delay from a conventional AND gate, different logical combinations of these OR and AND gates can produce significantly different path delays.